1. Field of the Invention
The present invention relates to an active matrix display construction and, more particularly, to a circuit and device structure for improving the quality of the image displayed on the viewing screen.
2. Description of the Related Art
FIG. 2(A) schematically shows a conventional active matrix display. In this figure, the region 204 surrounded by the broken line is a display region. Thin-film transistors 201 (only one is shown) are arranged in rows and columns in this region 204. Conductive interconnects connected with the source electrodes of the thin-film transistors 201 are image signal lines or data signal lines 206. Conductive interconnects connected with the gate electrodes of the thin-film transistors 201 are gate-selecting signal lines 205 (only one is shown).
We now take notice of driver devices. The thin-film transistors 201 act to switch data, and drive a liquid-crystal cell 203. Auxiliary capacitors 202 (only one is shown) are used to reinforce the capacitance OF the liquid-crystal cell, and act to hold image data. The thin-film transistors 201 are employed to switch image data indicated by the voltage applied across the liquid-crystal material. Let VGS be the gate voltage of each thin-film transistor. Let ID be the drain current. The relation VGS -ID is shown in FIG. 3. In particular, if the gate voltage VGS is in the cutoff region of the thin-film transistor, the drain current ID is increased, and it is called OFF current.
In the case of an N-channel thin-film transistor, the OFF current flowing when the gate voltage VGS is biased negatively is stipulated by the current flowing through a PN junction formed between a P-type layer and an N-type layer. The P-type layer is induced in the surface of the thin-film semiconductor. The N-type layer is formed in the source and drain regions. Because numerous traps exist in the thin-film transistor, this PN junction is incomplete and so the junction tends to produce a leakage current. As the gate electrode is biased more negatively, the OFF current is increased, for the following reason. The concentration of carriers in the P-type layer formed in the surface of the thin-film semiconductor is increased, thus reducing the width of the energy barrier in the PN junction. As a result, the electric field is concentrated, so that the current leaking from the junction increases.
The OFF current produced in this way depends greatly on the source/drain voltage. For example, it is known that as the voltage applied between the source and drain of a thin-film transistor is increased, the OFF current is increased drastically. That is, the OFF current produced when a voltage of 10 V is applied is not merely twice as large as the OFF current produced when a voltage of 5 V is applied between the source and drain. Rather, the ratio of the former OFF current to the latter OFF current reaches 10 or even 100. This nonlinearlity also depends on the gate voltage. Generally, where the reverse bias applied to the gate electrode is large (in the case of an N-channel type, a large negative voltage), the ratio is large.
In an attempt to solve this problem, the multi-gate method has been proposed as described in Japanese Patent Publication Nos. 44195/1993 and 44196/1993. In this method, thin-film transistors are connected in series. This method is intended to reduce the OFF current of each individual thin-film transistor, by reducing the voltage applied between the source and drain of each thin-film transistor. For example, where two-thin-film transistors are connected in series as shown in FIG. 2(B), the voltage applied between the source and drain of each thin-film transistor is halved. This reduces the OFF current by a factor of 10 or even 100 because of the principle described above.
TFTS, source lines, and gate lines are formed in an active matrix circuit. These elements hinder transmission of light. Specifically, the ratio (aperture ratio) of the area of the region that can be used for image display to the whole area is small. Typically, the aperture ratio is 30 to 60%. Especially, in a backlit display device. comprising an active matrix circuit backlit with intense light, if the aperture ratio is small, a major portion of the incident light is absorbed by TFTs and by the liquid-crystal material and so these TFTs and liquid-crystal material get hot. As a result, their characteristics are deteriorated.
However, as the image displayed on a liquid crystal display is required to have stricter characteristics, it is more difficult to reduce the OFF current by a required amount by the aforementioned multi-gate method. In particular, if the number of the gate electrodes (or, the number of thin-film transistors) is increased to 3, 4, and 5, then the voltage applied between the source and drain of each TFT decreases to one-third, one-fourth, and one-fifth, respectively. In this way, the latter voltage does not decrease rapidly. Therefore, in order to reduce the voltage between the source and drain by a factor of 100, as many as 100 gates are needed. That is, in this method, the resulting advantage is most conspicuous where the number of gates is two. However, if more gates are provided, great advantages cannot be expected.
In view of the foregoing problems, the present invention has been made.
It is an object of the invention to provide a pixel circuit which reduces the voltage applied between the source and drain of each TFT (thin-film transistor) connected with a pixel electrode down to a level which is about less than one-tenth, preferably less than one-hundredth, of the level normally obtained, thus reducing the OFF current. This pixel circuit is characterized in that the number of TFTs used for the above-described object is reduced sufficiently. Preferably, the number of the TFTs is less than 5, more preferably 3.
It is another object of the invention to provide an active matrix display comprising TFTs which are prevented from being irradiated with light without lowering the aperture ratio.
The theory underlying the inventive concept is illustrated in FIG. 2(C), where TFTs (thin-film transistors) 221 and 222 are connected in series. A capacitor 223 is inserted between these TFTs 221 and 222 to lower the voltage produced between the source and drain of the TFT 222 especially located on the side of a pixel electrode. This reduces the OFF current of the TFT 222. The illustrated capacitor 224 is not always necessary. Rather, this capacitor 224 increases the burden-imposed during writing. Therefore, if the ratio of the capacitance of a pixel cell 225 to the capacitance 223 is appropriate, then it may be desired to dispense with the capacitor 224.
The operation is next described in detail. When a select signal is sent to a gate signal line 226, both TFTs 221 and 222 are turned ON. Depending on the signal on an image signal line 227, the capacitors 223, 224 and the pixel cell 225 are electrically charged. When they are fully charged, i.e., when a balanced state is obtained, the voltage applied to the source of the TFT 222 is substantially equal to the voltage applied to the drain of the TFT 222.
Under this condition, if the select signal is made to cease, both TFTs 221 and 222 are turned OFF. Then, a signal for other pixel is applied to the image signal line 227. The TFT 221 produces a finite amount of leakage current. Consequently, the electric charge stored in the capacitor 223 is released, so that the voltage drops but at a rate roughly equal to the rate at which the voltage developed across the capacitor 202 of the normal active matrix circuit shown in FIG. 2(A) drops.
On the other hand, with respect to the TFT 222, the voltage developed between the source and drain is initially almost zero. For this reason, the OFF current is quite weak. Then, the voltage developed across the capacitor 223 drops. Therefore, the voltage between the source and drain increases gradually. This, in turn, increases the OFF current. Obviously, increases in the OFF current lower the voltage developed across the pixel cell 225 sufficiently more mildly than in the case of the normal active matrix circuit shown in FIG. 2(A).
For example, it is assumed that the TFTs 201 and 221 have similar characteristics and that the voltage developed across the capacitor 202 changes from 10 V to 9, V or 90%, during one frame. In the case illustrated in FIG. 2(A), the voltage developed across the pixel cell 203 drops down to 9 V during one frame. However, in the case illustrated in FIG. 2(C), even if the voltage developed across the capacitor 223 drops to 9, V the OFF current is quite small because the voltage between the source and drain of the TFT 222 is 1 V. This holds true when one frame ends. Consequently, the accumulated amount of electric charge released from the pixel cell 225 and from the capacitor 224 is quite small. Hence, the voltage developed across the pixel cell 225 is substantially maintained at 10 V.
It is not easy to compare the case illustrated in FIG. 2(A) with the case illustrated in FIG. 2(B). In FIG. 2(B), the voltage applied between the source and drain of one TFT is half (or 5 V) of the voltage (10 V) applied in the case of FIG. 2(A). It is unlikely that the voltage between the source and drain is 1 V, unlike the case of TFT 222 shown in FIG. 2(C). This is one advantage of the present invention.
If LDD regions or offset regions are inserted in the channels of the TFTs 221 and 222, then these regions form drain resistors and source resistors, respectively. This mitigates the electric field strength at the drain junction. Obviously, this reduces the OFF current further.
If a combination of TFTs and capacitors is added as shown in FIG. 2(D), then greater effect can be produced. However, the rate at which the effect is increased is lower than in the case in which the configuration shown in FIG. 2(A) is replaced by the configuration shown in FIG. 2(C).
In the above-described structure, the capacitors 223 and 224 can be ordinary capacitors. If one or both of them are MOS capacitors, then integration can be accomplished more efficiently. As mentioned previously, the capacitor 224 is not always necessary. If a lightly doped region is formed between the TFTs 221 and 222 to form a circuit configuration in which a resistor is inserted in series, then the OFF current can be reduced further.
Each capacitor consists of a fixed capacitor comprising two opposite metal electrodes. Instead, each capacitor may consist of a MOS capacitor formed by laminating a gate-insulating film and a gate electrode on a substantially intrinsic semiconductor film. The MOS capacitor is characterized in that the capacitance is varied by the potential at the gate electrode.
In one example of the MOS capacitor, three or more TFTs are connected in series with each one pixel electrode. At least one of them excluding those of the series connected TFTs which are located at opposite ends is maintained in conduction and used as a capacitor. In another example, a MOS capacitor is connected to the junction of the drain of one of the TFTs connected in series and the source of the other TFT. A stable electrostatic capacitance is obtained by maintaining the gate electrode of the MOS capacitor at an appropriate potential.
The present invention is characterized in that source lines are formed so as to cover channels in TFTs. The TFTs can be the top gate type obtained by forming a thin-film semiconductor region, gate lines (gate electrodes), an interlayer insulator, and source lines in this order. Alternatively, the TFTs can be the bottom gate type obtained by forming gate lines (gate electrodes), a thin-film semiconductor region, an interlayer insulator, and source lines in this order. It is to be noted that an ordinary active matrix circuit using bottom gate TFTs has no interlayer insulator. In the present invention, however, an interlayer insulator is needed to provide insulation between channel and source lines.
FIGS. 21 and 22 show conventional arrangements of TFTs in active matrix circuits. Gate lines 19 (only one is shown) and source lines 21 (only one is shown) are arranged so as to cross each other substantially at right angles. Branch lines 20 (only one is shown) extend from the gate lines and are made to overlap thin-film semiconductor regions. Thus, the branch lines 20 are used as gate electrodes of TFTs. At one end of each thin-film semiconductor region, a pixel electrode 22 and a contact 25 are formed. At the other end, a source line and a contact 24 are formed.
That portion of each thin-film semiconductor region which substantially overlaps the gate line is a channel 23. As shown in FIGS. 21 and 22, the channel 23 is widely spaced from the source line 21. The branch line 20 from the gate line increases the area occupied by the TFT, thus deteriorating the aperture ratio.
In the present invention, any structure corresponding to the branch line 20 is not formed. A channel is formed under a source line. This reduces the area occupied by the TFT. Also, the aperture ratio can be enhanced. The channel in a TFT is easily affected by light. Therefore, the whole TFT is normally enclosed. Furthermore, a light-shielding film is formed. This further lowers the aperture ratio. In the present invention, a source line is formed so as to cover the channel, thus shielding the channel from extraneous light. Consequently, it is not necessary to form a light-shielding film. This is quite effective in enhancing the aperture ratio.
The active matrix circuit of this construction is quite advantageously used for a backlit display device. As described above, a backlit display device is required to have a high aperture ratio. In addition, the device is illuminated with intense light. Hence, it is imperative that TFTs be shielded from light. In the present invention, light is projected from above source lines. This assures that the source lines shield the channels in the TFTs from light.
Other objects and features of the invention will appear in the course of the description thereof, which follows.